Lauterbach GmbH

Others

• Intel® Processor Trace

• RISC-V Trace

• Tessent Embedded Analytics Trace Solution for RISC-V

• System Trace

• TriCore AGBT with Serial Preprocessor

• Parallel trace port with up to 200 MBit/s per pin
• Configurable trace port width (4-, 8-, 12- or 16-bit)
• Standardized MIPI60 connector to target
• Includes AutoFocus Self Calibration technology
• Multicore tracing
• Up to 8 GByte trace memory
• Standard trace filters and triggers
• Comprehensive profiling
• Trace-based code coverage

Proprietary SiFive Nexus Trace Solution for RISC-V

• SiFive cores only
• Based on Nexus message protocol
• Instruction trace
• Trace protocol may include timestamps
• Multicore tracing
• Support for pure SiFive trace infrastructure or SiFive trace IP integrated into an Arm CoreSight trace infrastructure

Tessent Embedded Analytics Trace Solution for RISC-V

• Compliant to Efficient Trace for RISC-V Version 1
• Instruction trace
• Data trace, if supported by the implemented trace IP
• Timestamps, if supported by the implemented trace IP
• Multicore tracing
• Trace filters allow to reduce the generation of trace messages
• Support for Tessent Embedded Analytics only trace infrastructure and Tessent Embedded Analytics trace IP integrated into an Arm CoreSight trace infrastructure

System Trace

• Support of onchip-tracing (Embedded Trace Buffer), no additional trace hardware required
• CombiProbe and PowerTrace II / III to be used for trace data directed to external trace port
• High-level decoding of hard- and software instrumentation messages

System traces refer to trace modules which output data in compliance with the MIPI System Trace Protocol version 1 (STPv1) or version 2 (STPv2). It is used to transport hardware or software instrumentation messages.

Currently Lauterbach supports two implementations of system trace modules: The System Trace MacroCell as CoreSight component by ARM and the System Trace Module by Texas Instruments.

TriCore AGBT with Serial Preprocessor

• Robust trace recording using Aurora
• Up to 6.25 GBit/s per lane
• Up to 4 lanes
• Up to 8 GByte trace memory
• Streaming to host storage
• Delay counter
• Fast search and download
• Code Coverage
• Performance Analysis

The AGBT high-speed serial trace supports core- and bus trace for TriCore AURIX devices. The trace can be used for error diagnosis in real-time critical environments as well as for performance and code coverage analysis.

Tracing of TriCore and GTM is supported.